We-Meta =AI-native Engineering IntelligenceCognitive InfrastructureMeta-SkillsCollective Intelligence
CHIP DESIGN / PD · MATH × CS × AI

Si Pham.
Chip Design / PD.
Intelligence by design.

My approach combines semiconductor engineering with mathematical thinking, computer science and AI. I focus on understanding the problem, making trade-offs explicit and improving the way engineering decisions are made.

Meta-skills × Cybernetics × RSIEngineering LoopsIndustrial Research

Hiring for Chip Design / PD? Let’s discuss your team’s technical challenges. Contact opens my LinkedIn profile.

The foundation for Design Intelligence

Career journey

Explore my professional background on LinkedIn.

LinkedIn ↗
EXPLORE MY APPROACHWE-META.AI
Causal graph, conceptual Chip Design / PD floorplan and engineering Copilot connected in a learning loop CAUSAL GRAPH CauseContextMechanismTrace cause → effect COPILOT Sĩ’s assistantAsk · Reason · Reflect FEEDBACK · LEARNING LOOP Chip Design / PD MATH CS EVIDENCE → LEARNING AI CONCEPTUAL FLOORPLAN · NOT A SILICON RESULT
Observe→Reason→Build→Learn↻
Chip Design / PD×MATHEMATICS×COMPUTER SCIENCE×ARTIFICIAL INTELLIGENCE

01 / THE THREAD THROUGH MY WORK

One continuing journey.
Three connected perspectives.

My direction grows from semiconductor engineering: understanding the design, reasoning about the problem, and improving how the work gets done.

01 / ENGINEERING

Chip Design / PD

The anchor of my professional direction. Timing, power, area and implementation trade-offs give intelligence a concrete engineering context.

TimingPPAImplementation
02 / FOUNDATIONS

Math × CS

My enduring interests in models, algorithms, graphs and optimization shape how I break down complex design problems.

GraphsAlgorithmsModels
03 / EVOLUTION

Design Intelligence

The direction I am exploring: connect design data, evidence and AI assistance to support clearer engineering decisions.

EvidenceAI workflowsRSI

META-SKILLS / LEARNING TO LEARN

Build the skills that improve every other skill.

Meta-skills connect technical knowledge to better engineering judgment. In Chip Design / PD, they turn each problem into an opportunity to strengthen both the design and the way we work.

01

Systems thinking

Connect timing, power, area and routability. Understand how a local change affects the wider design.

02

Problem framing

Define the question, assumptions and constraints before choosing a tool or proposing a fix.

03

Evidence-based reasoning

Separate observations from hypotheses. Ask what evidence would support or challenge the explanation.

04

Learning & reflection

Review each experiment, extract a reusable lesson and improve the next iteration. This is the bridge to RSI.

FOUR COMPLEMENTARY WAYS TO THINK

Follow the sequence. See the system.
Explore interactions. Revisit the frame.

My proposed working framework connects meta-skills, cybernetics and Recursive Self-Improvement: develop how we think, organize feedback, then improve the learning loop itself.

01 / LINEAR

Linear thinking

Follow an explicit sequence of steps. In a design flow, trace inputs, constraints, transformations and reports to locate where a result changes.

02 / SYSTEMS

Systems thinking

Map dependencies and feedback. Consider how a timing intervention interacts with power, area, congestion and the rest of the flow.

03 / NONLINEAR

Nonlinear thinking

Investigate interactions, thresholds and sensitivity. Test whether a small configuration change produces a disproportionate effect instead of assuming a proportional response.

04 / META

Meta thinking

Examine the frame behind the decision. Are we optimizing the right objective? What assumptions shape the diagnosis? How should the method change?

These are complementary lenses, not a ranking. Choose the mode that fits the question and validate the result.

PROFESSIONAL BACKGROUND

For my career history, roles and professional connections, visit my LinkedIn profile.

View profile ↗

02 / AN INTERACTIVE ENGINEERING NOTE

Better questions.
Before bigger conclusions.

A small, working example of the approach: compare two design runs, inspect the trade-off, and separate an observation from a sign-off decision.

Timing trade-off explorer
ILLUSTRATIVE DATA

Compare a synthetic candidate against the same baseline. Values are teaching examples, not results from a customer design or an EDA run.

BASELINE / SETUPWNS −120 psTNS −2,400 ps · Area 100,000 µm²
WNS
TNS
CELL AREA
Baseline
−120 ps
Candidate
Bar length = magnitude of negative WNS. Shorter is better for this metric.
OBSERVATION ≠ SIGN-OFF

What would I check next?

Validate comparable constraints and tool settings; inspect critical paths; check hold timing and all relevant modes/corners; review congestion, power and physical verification. A better setup metric alone does not establish overall design closure.

Built as a public demonstration for we-meta.ai. No confidential design data. No AI model is used in this calculator.

ENGINEERING LOOPS / INDUSTRIAL RESEARCH

Close the loop.
Deepen the investigation.

The engineering standard I aim for: frame a consequential question, investigate deeply enough to support a decision, and close the loop with measurable evidence. Research earns its place through what it helps us understand, test and improve.

A result is one observation. A closed loop turns it into learning.

Without comparison and feedback, activity can repeat without progress. A useful loop connects an objective, an observed state, an intervention and a measured outcome—with a decision about what changes next.

01 / EXECUTION LOOP

Improve the design

Baseline → hypothesis → controlled change → run → compare → accept, revise or reject.

Chip Design / PD: investigate a timing regression, test an intervention, then check whether the wider PPA and verification constraints still hold.
02 / RESEARCH LOOP

Improve the explanation

Question → sources → competing explanations → experiment → evidence → updated understanding.

Read reports, relevant literature and technical documentation. Turn an explanation into a prediction that an experiment can challenge.
03 / META / RSI LOOP

Improve the method

Review repeated outcomes → find a weakness in the process → revise the method → evaluate the next cycle.

Improve the questions, data schema, experiment design or evaluation rubric—not just the configuration of the next run.

RESEARCH → DEEP RESEARCH → ENGINEERING DECISION

Depth that serves an industrial decision.

My proposed deep-research workflow brings technical literature and implementation evidence into the same investigation. The depth should match the uncertainty, impact and reversibility of the decision.

  1. Frame the decision. Define the problem, constraints, baseline, unknowns and acceptance criteria.
  2. Build an evidence map. Connect primary sources, reports and measurements; record versions, applicability and gaps.
  3. Challenge the explanation. Compare alternative hypotheses, seek counterexamples and identify what could falsify the leading view.
  4. Test against implementation. Design a reproducible experiment; account for modes, corners, runtime, compute cost and integration constraints.
  5. Deliver a decision package. State the recommendation, supporting evidence, limitations, unresolved risks and next validation step.
WHAT MAKES THE WORK REVIEWABLE

A research brief · source and evidence map · experiment record · comparison of alternatives · decision memo · follow-up measurement.

This describes the approach I am developing, not a claim of completed industrial engagements. Public examples use shareable or synthetic data; outcomes must be demonstrated in their actual context.

Discuss a challenging engineering problem ↗

03 / ENGINEERING NOTES

From a report
to a defensible decision.

Technical perspectives on Chip Design / PD, reproducible experiments and AI-assisted reasoning. These are method notes, not claims of client results or tape-out experience.

N.01CHIP DESIGN / PDWhat a timing improvement does—and does not—tell us

A lower magnitude of negative WNS is a useful observation. It does not explain the cause of the improvement, show the distribution of failing paths, or establish that the design is ready for sign-off.

Establish a comparable baseline

Record the design revision, constraints, library corner, analysis mode, flow stage and tool settings. Comparing pre-route and post-route reports without that context can hide differences in parasitic modeling.

Inspect the trade-off

Review WNS together with TNS and violating endpoints. Inspect setup and hold, cell and net delay, transition and capacitance, then consider area, power and routability. A positive change in one metric can move a problem elsewhere.

Decision record: what changed, which reports support it, what remains unresolved, and which check comes next.

Reference: OpenROAD Flow Tutorial ↗

N.02DATA-READY ENGINEERINGMake every design experiment traceable

A folder of reports becomes useful engineering data when each result can be traced to its inputs, configuration and intended question. A small, consistent run record is a practical starting point.

run_iddesign_revisionflow_stagemode / cornerconstraints_revisiontool_versionconfigurationmetrics + unitsreport_references

Preserve the evidence

Keep original reports alongside parsed values. Distinguish missing data from zero, normalize units, and record parser versions. A metric without its report reference is difficult to audit.

Make comparisons explainable

Define the intended intervention before running the experiment. Track other changed inputs and nondeterminism. Re-run when needed before attributing an observed improvement to a specific change.

Data-ready begins with provenance and comparability. A database or embedding index alone cannot provide them.

Reference: OpenROAD flow metrics ↗

N.03DESIGN INTELLIGENCE / RSIGive a copilot evidence before giving it authority

My proposed copilot workflow starts with a bounded engineering question. The assistant should distinguish a reported measurement, an inferred explanation and a suggested intervention.

  1. Retrieve: identify the relevant run, report, path and analysis context.
  2. Ground: attach source references to observations; mark missing evidence.
  3. Reason: propose hypotheses and the checks that could disprove them.
  4. Review: let the engineer evaluate the proposed action and its scope.
  5. Learn: compare the outcome with the expectation and update the method.
Evaluation proposal: source accuracy, numerical consistency, appropriate uncertainty and usefulness of the next check. This is a design direction; no production copilot is offered on this site yet.

FOR RECRUITERS & ENGINEERING TEAMS

Start with the engineering context.

For a focused conversation, share the role or project, the design stage, the main technical challenge and the expected contribution. My career history is available on LinkedIn; these notes show the direction of my thinking.

Discuss a role or project ↗

04 / BUILDING IN CONTINUITY

A focused beginning.
A longer horizon.

we-meta.ai begins with my engineering practice. The ambition is to turn useful methods into learning experiences, intelligence systems and services.

NOW / FIRST EDITION

Make the work visible

A professional home, an interactive Chip Design / PD note and a direct way to connect. A foundation for sharing further work as it develops.

NEXT / PLANNED

Learn through practice

Chip-design labs, technical notes, meta-skills and coaching. Graph thinking and iterative learning connected to real problems.

HORIZON / EXPLORING

Build design intelligence

Copilots, knowledge graphs, X Tensor and digital twins. Data-ready, infra-ready and AI-ready services for individuals and teams.

∞

RECURSIVE SELF-IMPROVEMENT

Improve the work. Then improve how you work.

Observe → form a hypothesis → test → examine evidence → update the method. This is the meaning of RSI I want to bring into everyday engineering practice.

LET’S CONNECT

Working on chips?
Let’s talk.

Connect with me about Chip Design / PD opportunities, semiconductor projects, or thoughtful ways to bring AI into engineering.

Message Si on LinkedIn ↗Recruiters · Engineering teams · Collaborators